ua1zbe
/
DMRGateway
mirror of https://github.com/g4klx/DMRGateway
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Add the status and exclusion PC/TG to the control ignore list.

This commit is contained in:
Jonathan Naylor 2020-04-13 20:53:05 +01:00
parent 4ab6ef030e
commit 3b3243c1bf
1 changed files with 7 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
RewriteDynTGRF.cpp
View File

@ -105,7 +105,7 @@ PROCESS_RESULT CRewriteDynTGRF::process(CDMRData& data, bool trace)
return RESULT_IGNORED; return RESULT_IGNORED;
} }
if (std::find(m_exclTGs.cbegin(), m_exclTGs.cend(), dstId) != m_exclTGs.cend()) { if (slotNo == m_slot && std::find(m_exclTGs.cbegin(), m_exclTGs.cend(), dstId) != m_exclTGs.cend()) {
if (trace) if (trace)
LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=%u: not matched", m_name.c_str(), m_slot, dstId); LogDebug("Rule Trace,\tRewriteDynTGRF from %s Slot=%u Dst=%u: not matched", m_name.c_str(), m_slot, dstId);
@ -156,6 +156,12 @@ void CRewriteDynTGRF::tgChange(unsigned int slot, unsigned int tg)
return; return;
} }
if (slot == m_slot && tg == m_statusPC)
return;
if (slot == m_slot && std::find(m_exclTGs.cbegin(), m_exclTGs.cend(), tg) != m_exclTGs.cend())
return;
if (slot == m_slot && tg >= m_fromTGStart && tg <= m_fromTGEnd) { if (slot == m_slot && tg >= m_fromTGStart && tg <= m_fromTGEnd) {
if (m_currentTG != tg) { if (m_currentTG != tg) {
m_currentTG = tg; m_currentTG = tg;