mirror of https://github.com/SQ9MDD/ESP32IGate.git
943 lines
28 KiB
C++
943 lines
28 KiB
C++
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#include <string.h>
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#include "AFSK.h"
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#include "Arduino.h"
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#include <Wire.h>
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#include <driver/adc.h>
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#include "esp_adc_cal.h"
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#include "cppQueue.h"
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#include "ButterworthFilter.h"
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extern "C"
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{
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#include "soc/syscon_reg.h"
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#include "soc/syscon_struct.h"
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}
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#define DEBUG_TNC
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extern unsigned long custom_preamble;
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extern unsigned long custom_tail;
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int adcVal;
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static const adc_unit_t unit = ADC_UNIT_1;
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void sample_isr();
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bool hw_afsk_dac_isr = false;
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Afsk *AFSK_modem;
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// //กรองความถี่สูงผ่าน >300Hz HPF Butterworth Filter. 0-300Hz ช่วงความถี่ต่ำใช้กับโทน CTCSS/DCS ในวิทยุสื่อสารจะถูกรองทิ้ง
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ButterworthFilter hp_filter(1300, 9600, ButterworthFilter::ButterworthFilter::Highpass, 1);
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// //กรองความถี่ต่ำผ่าน <3KHz LPF Butterworth Filter. ความถี่เสียงที่มากกว่า 3.5KHz ไม่ใช่ความถี่เสียงคนพูดจะถูกกรองทิ้ง
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// ButterworthFilter lp_filter(3500, 9600, ButterworthFilter::ButterworthFilter::Lowpass, 2);
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// // Bandpass Filter
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// void bandpass_filter(float *h, int n)
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// {
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// int i = 0;
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// for (i = 0; i < n; i++)
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// {
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// h[i] = lp_filter.Update(h[i]);
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// }
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// for (i = 0; i < n; i++)
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// {
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// h[i] = hp_filter.Update(h[i]);
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// }
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// }
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uint8_t CountOnesFromInteger(uint8_t value)
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{
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uint8_t count;
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for (count = 0; value != 0; count++, value &= value - 1)
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;
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return count;
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}
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#define IMPLEMENTATION FIFO
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#ifndef I2S_INTERNAL
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cppQueue adcq(sizeof(int8_t), 19200, IMPLEMENTATION); // Instantiate queue
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#endif
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// Forward declerations
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int afsk_getchar(void);
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void afsk_putchar(char c);
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#ifdef I2S_INTERNAL
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#define ADC_PATT_LEN_MAX (16)
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#define ADC_CHECK_UNIT(unit) RTC_MODULE_CHECK(adc_unit < ADC_UNIT_2, "ADC unit error, only support ADC1 for now", ESP_ERR_INVALID_ARG)
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#define RTC_MODULE_CHECK(a, str, ret_val) \
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if (!(a)) \
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{ \
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ESP_LOGE(RTC_MODULE_TAG, "%s:%d (%s):%s", __FILE__, __LINE__, __FUNCTION__, str); \
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return (ret_val); \
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}
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i2s_event_t i2s_evt;
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static QueueHandle_t i2s_event_queue;
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static esp_err_t adc_set_i2s_data_len(adc_unit_t adc_unit, int patt_len)
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{
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ADC_CHECK_UNIT(adc_unit);
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RTC_MODULE_CHECK((patt_len < ADC_PATT_LEN_MAX) && (patt_len > 0), "ADC pattern length error", ESP_ERR_INVALID_ARG);
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// portENTER_CRITICAL(&rtc_spinlock);
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if (adc_unit & ADC_UNIT_1)
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{
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SYSCON.saradc_ctrl.sar1_patt_len = patt_len - 1;
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}
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if (adc_unit & ADC_UNIT_2)
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{
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SYSCON.saradc_ctrl.sar2_patt_len = patt_len - 1;
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}
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// portEXIT_CRITICAL(&rtc_spinlock);
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return ESP_OK;
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}
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static esp_err_t adc_set_i2s_data_pattern(adc_unit_t adc_unit, int seq_num, adc_channel_t channel, adc_bits_width_t bits, adc_atten_t atten)
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{
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ADC_CHECK_UNIT(adc_unit);
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if (adc_unit & ADC_UNIT_1)
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{
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RTC_MODULE_CHECK((adc1_channel_t)channel < ADC1_CHANNEL_MAX, "ADC1 channel error", ESP_ERR_INVALID_ARG);
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}
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RTC_MODULE_CHECK(bits < ADC_WIDTH_MAX, "ADC bit width error", ESP_ERR_INVALID_ARG);
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RTC_MODULE_CHECK(atten < ADC_ATTEN_MAX, "ADC Atten Err", ESP_ERR_INVALID_ARG);
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// portENTER_CRITICAL(&rtc_spinlock);
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// Configure pattern table, each 8 bit defines one channel
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//[7:4]-channel [3:2]-bit width [1:0]- attenuation
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// BIT WIDTH: 3: 12BIT 2: 11BIT 1: 10BIT 0: 9BIT
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// ATTEN: 3: ATTEN = 11dB 2: 6dB 1: 2.5dB 0: 0dB
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uint8_t val = (channel << 4) | (bits << 2) | (atten << 0);
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if (adc_unit & ADC_UNIT_1)
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{
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SYSCON.saradc_sar1_patt_tab[seq_num / 4] &= (~(0xff << ((3 - (seq_num % 4)) * 8)));
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SYSCON.saradc_sar1_patt_tab[seq_num / 4] |= (val << ((3 - (seq_num % 4)) * 8));
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}
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if (adc_unit & ADC_UNIT_2)
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{
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SYSCON.saradc_sar2_patt_tab[seq_num / 4] &= (~(0xff << ((3 - (seq_num % 4)) * 8)));
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SYSCON.saradc_sar2_patt_tab[seq_num / 4] |= (val << ((3 - (seq_num % 4)) * 8));
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}
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// portEXIT_CRITICAL(&rtc_spinlock);
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return ESP_OK;
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}
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void I2S_Init(i2s_mode_t MODE, i2s_bits_per_sample_t BPS)
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{
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i2s_config_t i2s_config = {
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.mode = (i2s_mode_t)(I2S_MODE_MASTER | I2S_MODE_RX | I2S_MODE_TX | I2S_MODE_DAC_BUILT_IN | I2S_MODE_ADC_BUILT_IN),
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.sample_rate = SAMPLE_RATE,
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.bits_per_sample = I2S_BITS_PER_SAMPLE_16BIT,
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.channel_format = I2S_CHANNEL_FMT_ALL_LEFT,
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.communication_format = (i2s_comm_format_t)I2S_COMM_FORMAT_I2S_MSB,
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.intr_alloc_flags = 0, // ESP_INTR_FLAG_LEVEL1,
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.dma_buf_count = 5,
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.dma_buf_len = 384,
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//.tx_desc_auto_clear = true,
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.use_apll = false // no Audio PLL ( I dont need the adc to be accurate )
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};
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if (MODE == I2S_MODE_RX || MODE == I2S_MODE_TX)
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{
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Serial.println("using I2S_MODE");
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i2s_pin_config_t pin_config;
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pin_config.bck_io_num = PIN_I2S_BCLK;
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pin_config.ws_io_num = PIN_I2S_LRC;
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if (MODE == I2S_MODE_RX)
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{
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pin_config.data_out_num = I2S_PIN_NO_CHANGE;
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pin_config.data_in_num = PIN_I2S_DIN;
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}
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else if (MODE == I2S_MODE_TX)
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{
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pin_config.data_out_num = PIN_I2S_DOUT;
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pin_config.data_in_num = I2S_PIN_NO_CHANGE;
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}
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i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL);
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i2s_set_pin(I2S_NUM_0, &pin_config);
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i2s_set_clk(I2S_NUM_0, SAMPLE_RATE, BPS, I2S_CHANNEL_MONO);
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}
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else if (MODE == I2S_MODE_DAC_BUILT_IN || MODE == I2S_MODE_ADC_BUILT_IN)
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{
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Serial.println("Using I2S DAC/ADC_builtin");
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// install and start i2s driver
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if (i2s_driver_install(I2S_NUM_0, &i2s_config, 5, &i2s_event_queue) != ESP_OK)
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{
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Serial.println("ERROR: Unable to install I2S drives");
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}
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// GPIO36, VP
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// init ADC pad
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i2s_set_adc_mode(ADC_UNIT_1, ADC1_CHANNEL_0);
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// i2s_set_clk(I2S_NUM_0, SAMPLE_RATE, BPS, I2S_CHANNEL_MONO);
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i2s_adc_enable(I2S_NUM_0);
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delay(500); // required for stability of ADC
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// ***IMPORTANT*** enable continuous adc sampling
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SYSCON.saradc_ctrl2.meas_num_limit = 0;
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// sample time SAR setting
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SYSCON.saradc_ctrl.sar_clk_div = 2;
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SYSCON.saradc_fsm.sample_cycle = 2;
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adc_set_i2s_data_pattern(ADC_UNIT_1, 0, ADC_CHANNEL_0, ADC_WIDTH_BIT_12, ADC_ATTEN_DB_0); // Input Vref 1.36V=4095,Offset 0.6324V=1744
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adc_set_i2s_data_len(ADC_UNIT_1, 1);
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i2s_set_pin(I2S_NUM_0, NULL);
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i2s_set_dac_mode(I2S_DAC_CHANNEL_LEFT_EN); // IO26
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i2s_zero_dma_buffer(I2S_NUM_0);
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// i2s_start(I2S_NUM_0);
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// dac_output_enable(DAC_CHANNEL_1);
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dac_output_enable(DAC_CHANNEL_2);
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dac_i2s_enable();
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}
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}
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#else
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hw_timer_t *timer = NULL;
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void AFSK_TimerEnable(bool sts)
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{
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if (sts == true)
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timerAlarmEnable(timer);
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else
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timerAlarmDisable(timer);
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}
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#endif
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void AFSK_hw_init(void)
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{
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// Set up ADC
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pinMode(RSSI_PIN, INPUT_PULLUP);
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pinMode(PTT_PIN, OUTPUT);
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pinMode(4, OUTPUT);
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pinMode(LED_PIN, OUTPUT);
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digitalWrite(LED_PIN, LOW);
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digitalWrite(PTT_PIN, LOW);
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#ifdef I2S_INTERNAL
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// Initialize the I2S peripheral
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I2S_Init(I2S_MODE_DAC_BUILT_IN, I2S_BITS_PER_SAMPLE_16BIT);
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#else
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pinMode(MIC_PIN, INPUT);
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// Init ADC and Characteristics
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// esp_adc_cal_characteristics_t characteristics;
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adc1_config_width(ADC_WIDTH_BIT_12);
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adc1_config_channel_atten(SPK_PIN, ADC_ATTEN_DB_0); // Input 1.24Vp-p,Use R 33K-(10K//10K) divider input power 1.2Vref
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// adc1_config_channel_atten(SPK_PIN, ADC_ATTEN_DB_11); //Input 3.3Vp-p,Use R 10K divider input power 3.3V
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// esp_adc_cal_get_characteristics(V_REF, ADC_ATTEN_DB_11, ADC_WIDTH_BIT_12, &characteristics);
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// Serial.printf("v_ref routed to 3.3V\n");
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// Start a timer at 9.6kHz to sample the ADC and play the audio on the DAC.
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timer = timerBegin(3, 10, true); // 80 MHz / 10 = 8MHz hardware clock
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timerAttachInterrupt(timer, &sample_isr, true); // Attaches the handler function to the timer
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timerAlarmWrite(timer, 834, true); // Interrupts when counter == 834, 9592.3 times a second
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// timerAlarmEnable(timer);
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#endif
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}
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void AFSK_init(Afsk *afsk)
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{
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// Allocate modem struct memory
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memset(afsk, 0, sizeof(*afsk));
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AFSK_modem = afsk;
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// Set phase increment
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afsk->phaseInc = MARK_INC;
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// Initialise FIFO buffers
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fifo_init(&afsk->delayFifo, (uint8_t *)afsk->delayBuf, sizeof(afsk->delayBuf));
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fifo_init(&afsk->rxFifo, afsk->rxBuf, sizeof(afsk->rxBuf));
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fifo_init(&afsk->txFifo, afsk->txBuf, sizeof(afsk->txBuf));
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// Fill delay FIFO with zeroes
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for (int i = 0; i < SAMPLESPERBIT / 2; i++)
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{
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fifo_push(&afsk->delayFifo, 0);
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}
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AFSK_hw_init();
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}
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static void AFSK_txStart(Afsk *afsk)
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{
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if (!afsk->sending)
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{
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afsk->phaseInc = MARK_INC;
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afsk->phaseAcc = 0;
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afsk->bitstuffCount = 0;
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afsk->sending = true;
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// LED_TX_ON();
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digitalWrite(LED_TX_PIN, HIGH);
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digitalWrite(PTT_PIN, HIGH);
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afsk->preambleLength = DIV_ROUND(custom_preamble * BITRATE, 9600);
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AFSK_DAC_IRQ_START();
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#ifdef I2S_INTERNAL
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i2s_zero_dma_buffer(I2S_NUM_0);
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dac_i2s_enable();
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#endif
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}
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noInterrupts();
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afsk->tailLength = DIV_ROUND(custom_tail * BITRATE, 9600);
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interrupts();
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}
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void afsk_putchar(char c)
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{
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AFSK_txStart(AFSK_modem);
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while (fifo_isfull_locked(&AFSK_modem->txFifo))
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{
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/* Wait */
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// delay(10);
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}
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fifo_push_locked(&AFSK_modem->txFifo, c);
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}
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int afsk_getchar(void)
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{
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if (fifo_isempty_locked(&AFSK_modem->rxFifo))
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{
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return EOF;
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}
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else
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{
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return fifo_pop_locked(&AFSK_modem->rxFifo);
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}
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}
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void AFSK_transmit(char *buffer, size_t size)
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{
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fifo_flush(&AFSK_modem->txFifo);
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int i = 0;
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while (size--)
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{
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afsk_putchar(buffer[i++]);
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}
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}
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uint8_t AFSK_dac_isr(Afsk *afsk)
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{
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if (afsk->sampleIndex == 0)
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{
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// LED_RX_ON();
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// digitalWrite(LED_PIN), LOW);
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if (afsk->txBit == 0)
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{
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if (fifo_isempty(&afsk->txFifo) && afsk->tailLength == 0)
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{
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AFSK_DAC_IRQ_STOP();
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afsk->sending = false;
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// LED_TX_OFF();
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// digitalWrite(PTT_PIN, LOW);
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return 0;
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}
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else
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{
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if (!afsk->bitStuff)
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afsk->bitstuffCount = 0;
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afsk->bitStuff = true;
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if (afsk->preambleLength == 0)
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{
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if (fifo_isempty(&afsk->txFifo))
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{
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afsk->tailLength--;
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afsk->currentOutputByte = HDLC_FLAG;
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}
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else
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{
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afsk->currentOutputByte = fifo_pop(&afsk->txFifo);
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}
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}
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else
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{
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afsk->preambleLength--;
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afsk->currentOutputByte = HDLC_FLAG;
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}
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if (afsk->currentOutputByte == AX25_ESC)
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{
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if (fifo_isempty(&afsk->txFifo))
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{
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AFSK_DAC_IRQ_STOP();
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afsk->sending = false;
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// LED_TX_OFF();
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// digitalWrite(PTT_PIN, LOW);
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return 0;
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}
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else
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{
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afsk->currentOutputByte = fifo_pop(&afsk->txFifo);
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}
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}
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else if (afsk->currentOutputByte == HDLC_FLAG || afsk->currentOutputByte == HDLC_RESET)
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{
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afsk->bitStuff = false;
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}
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}
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afsk->txBit = 0x01;
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}
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if (afsk->bitStuff && afsk->bitstuffCount >= BIT_STUFF_LEN)
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{
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afsk->bitstuffCount = 0;
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afsk->phaseInc = SWITCH_TONE(afsk->phaseInc);
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}
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else
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{
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if (afsk->currentOutputByte & afsk->txBit)
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{
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afsk->bitstuffCount++;
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}
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else
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{
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afsk->bitstuffCount = 0;
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afsk->phaseInc = SWITCH_TONE(afsk->phaseInc);
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}
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afsk->txBit <<= 1;
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}
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afsk->sampleIndex = SAMPLESPERBIT;
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}
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afsk->phaseAcc += afsk->phaseInc;
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afsk->phaseAcc %= SIN_LEN;
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if (afsk->sampleIndex > 0)
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afsk->sampleIndex--;
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// LED_RX_OFF();
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return sinSample(afsk->phaseAcc);
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}
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int hdlc_flag_count = 0;
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bool hdlc_flage_end = false;
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static bool hdlcParse(Hdlc *hdlc, bool bit, FIFOBuffer *fifo)
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{
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// Initialise a return value. We start with the
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// assumption that all is going to end well :)
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bool ret = true;
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// Bitshift our byte of demodulated bits to
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// the left by one bit, to make room for the
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// next incoming bit
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hdlc->demodulatedBits <<= 1;
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// And then put the newest bit from the
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// demodulator into the byte.
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hdlc->demodulatedBits |= bit ? 1 : 0;
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// Now we'll look at the last 8 received bits, and
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// check if we have received a HDLC flag (01111110)
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if (hdlc->demodulatedBits == HDLC_FLAG)
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{
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// If we have, check that our output buffer is
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// not full.
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if (!fifo_isfull(fifo))
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{
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// If it isn't, we'll push the HDLC_FLAG into
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// the buffer and indicate that we are now
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// receiving data. For bling we also turn
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// on the RX LED.
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fifo_push(fifo, HDLC_FLAG);
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hdlc->receiving = true;
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if (++hdlc_flag_count >= 3)
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{
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LED_RX_ON();
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}
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}
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else
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{
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// If the buffer is full, we have a problem
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// and abort by setting the return value to
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// false and stopping the here.
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ret = false;
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hdlc->receiving = false;
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LED_RX_OFF();
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hdlc_flag_count = 0;
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|
hdlc_flage_end = false;
|
|
}
|
|
|
|
// Everytime we receive a HDLC_FLAG, we reset the
|
|
// storage for our current incoming byte and bit
|
|
// position in that byte. This effectively
|
|
// synchronises our parsing to the start and end
|
|
// of the received bytes.
|
|
hdlc->currentByte = 0;
|
|
hdlc->bitIndex = 0;
|
|
return ret;
|
|
}
|
|
|
|
// Check if we have received a RESET flag (01111111)
|
|
// In this comparison we also detect when no transmission
|
|
// (or silence) is taking place, and the demodulator
|
|
// returns an endless stream of zeroes. Due to the NRZ
|
|
// coding, the actual bits send to this function will
|
|
// be an endless stream of ones, which this AND operation
|
|
// will also detect.
|
|
if ((hdlc->demodulatedBits & HDLC_RESET) == HDLC_RESET)
|
|
{
|
|
// If we have, something probably went wrong at the
|
|
// transmitting end, and we abort the reception.
|
|
hdlc->receiving = false;
|
|
LED_RX_OFF();
|
|
hdlc_flag_count = 0;
|
|
hdlc_flage_end = false;
|
|
return ret;
|
|
}
|
|
|
|
// If we have not yet seen a HDLC_FLAG indicating that
|
|
// a transmission is actually taking place, don't bother
|
|
// with anything.
|
|
if (!hdlc->receiving)
|
|
return ret;
|
|
|
|
hdlc_flage_end = true;
|
|
|
|
// First check if what we are seeing is a stuffed bit.
|
|
// Since the different HDLC control characters like
|
|
// HDLC_FLAG, HDLC_RESET and such could also occur in
|
|
// a normal data stream, we employ a method known as
|
|
// "bit stuffing". All control characters have more than
|
|
// 5 ones in a row, so if the transmitting party detects
|
|
// this sequence in the _data_ to be transmitted, it inserts
|
|
// a zero to avoid the receiving party interpreting it as
|
|
// a control character. Therefore, if we detect such a
|
|
// "stuffed bit", we simply ignore it and wait for the
|
|
// next bit to come in.
|
|
//
|
|
// We do the detection by applying an AND bit-mask to the
|
|
// stream of demodulated bits. This mask is 00111111 (0x3f)
|
|
// if the result of the operation is 00111110 (0x3e), we
|
|
// have detected a stuffed bit.
|
|
if ((hdlc->demodulatedBits & 0x3f) == 0x3e)
|
|
return ret;
|
|
|
|
// If we have an actual 1 bit, push this to the current byte
|
|
// If it's a zero, we don't need to do anything, since the
|
|
// bit is initialized to zero when we bitshifted earlier.
|
|
if (hdlc->demodulatedBits & 0x01)
|
|
hdlc->currentByte |= 0x80;
|
|
|
|
// Increment the bitIndex and check if we have a complete byte
|
|
if (++hdlc->bitIndex >= 8)
|
|
{
|
|
// If we have a HDLC control character, put a AX.25 escape
|
|
// in the received data. We know we need to do this,
|
|
// because at this point we must have already seen a HDLC
|
|
// flag, meaning that this control character is the result
|
|
// of a bitstuffed byte that is equal to said control
|
|
// character, but is actually part of the data stream.
|
|
// By inserting the escape character, we tell the protocol
|
|
// layer that this is not an actual control character, but
|
|
// data.
|
|
if ((hdlc->currentByte == HDLC_FLAG ||
|
|
hdlc->currentByte == HDLC_RESET ||
|
|
hdlc->currentByte == AX25_ESC))
|
|
{
|
|
// We also need to check that our received data buffer
|
|
// is not full before putting more data in
|
|
if (!fifo_isfull(fifo))
|
|
{
|
|
fifo_push(fifo, AX25_ESC);
|
|
}
|
|
else
|
|
{
|
|
// If it is, abort and return false
|
|
hdlc->receiving = false;
|
|
LED_RX_OFF();
|
|
hdlc_flag_count = 0;
|
|
ret = false;
|
|
#ifdef DEBUG_TNC
|
|
Serial.println("FIFO IS FULL");
|
|
#endif
|
|
}
|
|
}
|
|
|
|
// Push the actual byte to the received data FIFO,
|
|
// if it isn't full.
|
|
if (!fifo_isfull(fifo))
|
|
{
|
|
fifo_push(fifo, hdlc->currentByte);
|
|
}
|
|
else
|
|
{
|
|
// If it is, well, you know by now!
|
|
hdlc->receiving = false;
|
|
LED_RX_OFF();
|
|
hdlc_flag_count = 0;
|
|
ret = false;
|
|
#ifdef DEBUG_TNC
|
|
Serial.println("FIFO IS FULL");
|
|
#endif
|
|
}
|
|
|
|
// Wipe received byte and reset bit index to 0
|
|
hdlc->currentByte = 0;
|
|
hdlc->bitIndex = 0;
|
|
}
|
|
else
|
|
{
|
|
// We don't have a full byte yet, bitshift the byte
|
|
// to make room for the next bit
|
|
hdlc->currentByte >>= 1;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
void AFSK_adc_isr(Afsk *afsk, int8_t currentSample)
|
|
{
|
|
/*
|
|
* Frequency discrimination is achieved by simply multiplying
|
|
* the sample with a delayed sample of (samples per bit) / 2.
|
|
* Then the signal is lowpass filtered with a first order,
|
|
* 600 Hz filter. The filter implementation is selectable
|
|
*/
|
|
|
|
// BUTTERWORTH Filter
|
|
// afsk->iirX[0] = afsk->iirX[1];
|
|
// afsk->iirX[1] = ((int8_t)fifo_pop(&afsk->delayFifo) * currentSample) / 6.027339492F;
|
|
// afsk->iirY[0] = afsk->iirY[1];
|
|
// afsk->iirY[1] = afsk->iirX[0] + afsk->iirX[1] + afsk->iirY[0] * 0.6681786379F;
|
|
|
|
//Fast calcultor
|
|
int16_t tmp16t;
|
|
afsk->iirX[0] = afsk->iirX[1];
|
|
tmp16t = (int16_t)((int8_t)fifo_pop(&afsk->delayFifo) * (int8_t)currentSample);
|
|
afsk->iirX[1] = (tmp16t >> 2) + (tmp16t >> 5);
|
|
afsk->iirY[0] = afsk->iirY[1];
|
|
tmp16t = (afsk->iirY[0] >> 2) + (afsk->iirY[0] >> 3) + (afsk->iirY[0] >> 4);
|
|
afsk->iirY[1] = afsk->iirX[0] + afsk->iirX[1] + tmp16t;
|
|
|
|
// We put the sampled bit in a delay-line:
|
|
// First we bitshift everything 1 left
|
|
afsk->sampledBits <<= 1;
|
|
// And then add the sampled bit to our delay line
|
|
afsk->sampledBits |= (afsk->iirY[1] > 0) ? 1 : 0;
|
|
|
|
// Put the current raw sample in the delay FIFO
|
|
fifo_push(&afsk->delayFifo, currentSample);
|
|
|
|
// We need to check whether there is a signal transition.
|
|
// If there is, we can recalibrate the phase of our
|
|
// sampler to stay in sync with the transmitter. A bit of
|
|
// explanation is required to understand how this works.
|
|
// Since we have PHASE_MAX/PHASE_BITS = 8 samples per bit,
|
|
// we employ a phase counter (currentPhase), that increments
|
|
// by PHASE_BITS everytime a sample is captured. When this
|
|
// counter reaches PHASE_MAX, it wraps around by modulus
|
|
// PHASE_MAX. We then look at the last three samples we
|
|
// captured and determine if the bit was a one or a zero.
|
|
//
|
|
// This gives us a "window" looking into the stream of
|
|
// samples coming from the ADC. Sort of like this:
|
|
//
|
|
// Past Future
|
|
// 0000000011111111000000001111111100000000
|
|
// |________|
|
|
// ||
|
|
// Window
|
|
//
|
|
// Every time we detect a signal transition, we adjust
|
|
// where this window is positioned little. How much we
|
|
// adjust it is defined by PHASE_INC. If our current phase
|
|
// phase counter value is less than half of PHASE_MAX (ie,
|
|
// the window size) when a signal transition is detected,
|
|
// add PHASE_INC to our phase counter, effectively moving
|
|
// the window a little bit backward (to the left in the
|
|
// illustration), inversely, if the phase counter is greater
|
|
// than half of PHASE_MAX, we move it forward a little.
|
|
// This way, our "window" is constantly seeking to position
|
|
// it's center at the bit transitions. Thus, we synchronise
|
|
// our timing to the transmitter, even if it's timing is
|
|
// a little off compared to our own.
|
|
if (SIGNAL_TRANSITIONED(afsk->sampledBits))
|
|
{
|
|
if (afsk->currentPhase < PHASE_THRESHOLD)
|
|
{
|
|
afsk->currentPhase += PHASE_INC;
|
|
}
|
|
else
|
|
{
|
|
afsk->currentPhase -= PHASE_INC;
|
|
}
|
|
}
|
|
|
|
// We increment our phase counter
|
|
afsk->currentPhase += PHASE_BITS;
|
|
|
|
// Check if we have reached the end of
|
|
// our sampling window.
|
|
if (afsk->currentPhase >= PHASE_MAX)
|
|
{
|
|
// If we have, wrap around our phase
|
|
// counter by modulus
|
|
afsk->currentPhase %= PHASE_MAX;
|
|
|
|
// Bitshift to make room for the next
|
|
// bit in our stream of demodulated bits
|
|
afsk->actualBits <<= 1;
|
|
|
|
//// Alternative using 5 bits ////////////////
|
|
uint8_t bits = afsk->sampledBits & 0x1f;
|
|
uint8_t c = CountOnesFromInteger(bits);
|
|
if (c >= 3)
|
|
afsk->actualBits |= 1;
|
|
/////////////////////////////////////////////////
|
|
|
|
// Now we can pass the actual bit to the HDLC parser.
|
|
// We are using NRZ coding, so if 2 consecutive bits
|
|
// have the same value, we have a 1, otherwise a 0.
|
|
// We use the TRANSITION_FOUND function to determine this.
|
|
//
|
|
// This is smart in combination with bit stuffing,
|
|
// since it ensures a transmitter will never send more
|
|
// than five consecutive 1's. When sending consecutive
|
|
// ones, the signal stays at the same level, and if
|
|
// this happens for longer periods of time, we would
|
|
// not be able to synchronize our phase to the transmitter
|
|
// and would start experiencing "bit slip".
|
|
//
|
|
// By combining bit-stuffing with NRZ coding, we ensure
|
|
// that the signal will regularly make transitions
|
|
// that we can use to synchronize our phase.
|
|
//
|
|
// We also check the return of the Link Control parser
|
|
// to check if an error occured.
|
|
|
|
if (!hdlcParse(&afsk->hdlc, !TRANSITION_FOUND(afsk->actualBits), &afsk->rxFifo))
|
|
{
|
|
afsk->status |= 1;
|
|
if (fifo_isfull(&afsk->rxFifo))
|
|
{
|
|
fifo_flush(&afsk->rxFifo);
|
|
afsk->status = 0;
|
|
#ifdef DEBUG_TNC
|
|
Serial.println("FIFO IS FULL");
|
|
#endif
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
#define ADC_SAMPLES_COUNT 192
|
|
int16_t abufPos = 0;
|
|
// extern TaskHandle_t taskSensorHandle;
|
|
|
|
extern void APRS_poll();
|
|
uint8_t poll_timer = 0;
|
|
// int adc_count = 0;
|
|
int offset_new = 0, offset = 2303, offset_count = 0;
|
|
|
|
#ifndef I2S_INTERNAL
|
|
// int x=0;
|
|
portMUX_TYPE DRAM_ATTR timerMux = portMUX_INITIALIZER_UNLOCKED;
|
|
|
|
void IRAM_ATTR sample_isr()
|
|
{
|
|
// portENTER_CRITICAL_ISR(&timerMux); // ISR start
|
|
|
|
if (hw_afsk_dac_isr)
|
|
{
|
|
uint8_t sinwave = AFSK_dac_isr(AFSK_modem);
|
|
// abufPos += 45;
|
|
// sinwave =(uint8_t)(127+(sin((float)abufPos/57)*128));
|
|
// if(abufPos>=315) abufPos=0;
|
|
// if(x++<16) Serial.printf("%d,",sinwave);
|
|
dacWrite(MIC_PIN, sinwave);
|
|
if (AFSK_modem->sending == false)
|
|
digitalWrite(PTT_PIN, LOW);
|
|
}
|
|
else
|
|
{
|
|
// digitalWrite(4, HIGH);
|
|
adcVal = adc1_get_raw(SPK_PIN); // Read ADC1_0 From PIN 36(VP)
|
|
// Auto offset level
|
|
offset_new += adcVal;
|
|
offset_count++;
|
|
if (offset_count >= 192)
|
|
{
|
|
offset = offset_new / offset_count;
|
|
offset_count = 0;
|
|
offset_new = 0;
|
|
if (offset > 3300 || offset < 1300) // Over dc offset to default
|
|
offset = 2303;
|
|
}
|
|
// Convert unsign wave to sign wave form
|
|
adcVal -= offset;
|
|
// adcVal-=2030;
|
|
int8_t adcR = (int8_t)((int16_t)(adcVal >> 4)); // Reduce 12bit to 8bit
|
|
// int8_t adcR = (int8_t)(adcVal / 16); // Reduce 12bit to 8bit
|
|
adcq.push(&adcR); // Add queue buffer
|
|
// digitalWrite(4, LOW);
|
|
}
|
|
// portEXIT_CRITICAL_ISR(&timerMux); // ISR end
|
|
}
|
|
#else
|
|
bool tx_en = false;
|
|
#endif
|
|
|
|
extern int mVrms;
|
|
extern float dBV;
|
|
extern bool afskSync;
|
|
|
|
long mVsum = 0;
|
|
int mVsumCount = 0;
|
|
long lastVrms=0;
|
|
bool VrmsFlag=false;
|
|
|
|
void AFSK_Poll()
|
|
{
|
|
int mV;
|
|
int x = 0;
|
|
// uint8_t sintable[8] = {127, 217, 254, 217, 127, 36, 0, 36};
|
|
#ifdef I2S_INTERNAL
|
|
size_t bytesRead;
|
|
uint16_t pcm_in[ADC_SAMPLES_COUNT];
|
|
uint16_t pcm_out[ADC_SAMPLES_COUNT];
|
|
#else
|
|
int8_t adc;
|
|
#endif
|
|
|
|
if (hw_afsk_dac_isr)
|
|
{
|
|
#ifdef I2S_INTERNAL
|
|
memset(pcm_out, 0, sizeof(pcm_out));
|
|
for (x = 0; x < ADC_SAMPLES_COUNT; x++)
|
|
{
|
|
// LED_RX_ON();
|
|
adcVal = (int)AFSK_dac_isr(AFSK_modem);
|
|
if (AFSK_modem->sending == false && adcVal == 0)
|
|
break;
|
|
|
|
//ไม่สามารถใช้งานในโหมด MONO ได้ จะต้องส่งข้อมูลตามลำดับซ้ายและขวา เอาต์พุต DAC บน I2S เป็นสเตอริโอเสมอ
|
|
// Ref: https://lang-ship.com/blog/work/esp32-i2s-dac/#toc6
|
|
// Left Channel GPIO 26
|
|
pcm_out[x] = (uint16_t)adcVal; // MSB
|
|
pcm_out[x] <<= 8;
|
|
x++;
|
|
// Right Channel GPIO 25
|
|
pcm_out[x] = 0;
|
|
pcm_out[x] = 0;
|
|
}
|
|
|
|
if (x > 0)
|
|
{
|
|
if (i2s_write_bytes(I2S_NUM_0, (char *)&pcm_out, (x * sizeof(uint16_t)), portMAX_DELAY) == ESP_OK)
|
|
{
|
|
Serial.println("I2S Write Error");
|
|
}
|
|
}
|
|
|
|
//รอให้ I2S DAC ส่งให้หมดบัพเฟอร์ก่อนสั่งปิด DAC/PTT
|
|
if (AFSK_modem->sending == false)
|
|
{
|
|
int txEvents = 0;
|
|
memset(pcm_out, 0, sizeof(pcm_out));
|
|
// Clear Delay DMA Buffer
|
|
for (int i = 0; i < 5; i++)
|
|
i2s_write_bytes(I2S_NUM_0, (char *)&pcm_out, (ADC_SAMPLES_COUNT * sizeof(uint16_t)), portMAX_DELAY);
|
|
// wait on I2S event queue until a TX_DONE is found
|
|
while (xQueueReceive(i2s_event_queue, &i2s_evt, portMAX_DELAY) == pdPASS)
|
|
{
|
|
if (i2s_evt.type == I2S_EVENT_TX_DONE) // I2S DMA finish sent 1 buffer
|
|
{
|
|
if (++txEvents > 6)
|
|
{
|
|
// Serial.println("TX DONE");
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
dac_i2s_disable();
|
|
i2s_zero_dma_buffer(I2S_NUM_0);
|
|
digitalWrite(PTT_PIN, LOW);
|
|
}
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
#ifdef I2S_INTERNAL
|
|
if (i2s_read(I2S_NUM_0, (char *)&pcm_in, (ADC_SAMPLES_COUNT * sizeof(uint16_t)), &bytesRead, portMAX_DELAY) == ESP_OK)
|
|
{
|
|
|
|
for (int i = 0; i < (bytesRead / sizeof(uint16_t)); i += 2)
|
|
{
|
|
adcVal = (int)pcm_in[i];
|
|
offset_new += adcVal;
|
|
offset_count++;
|
|
if (offset_count >= 192) //192
|
|
{
|
|
offset = offset_new / offset_count;
|
|
offset_count = 0;
|
|
offset_new = 0;
|
|
if (offset > 3300 || offset < 1300) // Over dc offset to default
|
|
offset = 2303;
|
|
}
|
|
adcVal -= offset; // Convert unsinewave to sinewave
|
|
|
|
float adcF=hp_filter.Update((float)adcVal);
|
|
adcVal=(int)adcF;
|
|
|
|
if (afskSync == false)
|
|
{
|
|
mV = abs((int)adcVal); // mVp-p
|
|
mV = (int)((float)mV / 3.68F); // mV=(mV*625)/36848;
|
|
mVsum += powl(mV, 2);
|
|
mVsumCount++;
|
|
}
|
|
//int8_t adcR = (int8_t)((int16_t)(adcVal >> 4)); // Reduce 12bit to 8bit
|
|
int8_t adcR=(int8_t)(adcVal/16);
|
|
|
|
AFSK_adc_isr(AFSK_modem, adcR); // Process signal IIR
|
|
if (i % 4 == 0)
|
|
APRS_poll(); // Poll check every 1 bit
|
|
}
|
|
// Get mVrms on Sync flage 0x7E
|
|
if (afskSync == false)
|
|
{
|
|
if (hdlc_flag_count > 3 && hdlc_flage_end == true)
|
|
{
|
|
if (mVsumCount > 960)
|
|
{
|
|
mVrms = sqrtl(mVsum / mVsumCount);
|
|
mVsum = 0;
|
|
mVsumCount = 0;
|
|
lastVrms=millis()+500;
|
|
VrmsFlag=true;
|
|
//if(millis()>lastVrms){
|
|
// double Vrms=(double)mVrms/1000;
|
|
// dBV = 20.0F * log10(Vrms);
|
|
// //dBu = 20 * log10(Vrms / 0.7746);
|
|
// Serial.printf("mVrms=%d dBV=%0.1f agc=%0.2f\n",mVrms,dBV);
|
|
//afskSync = true;
|
|
//}
|
|
}
|
|
}
|
|
if(millis()>lastVrms && VrmsFlag){
|
|
afskSync = true;
|
|
VrmsFlag=false;
|
|
}
|
|
}
|
|
}
|
|
#else
|
|
if (adcq.getCount() >= ADC_SAMPLES_COUNT)
|
|
{
|
|
for (x = 0; x < ADC_SAMPLES_COUNT; x++)
|
|
{
|
|
if (!adcq.pop(&adc)) // Pull queue buffer
|
|
break;
|
|
// audiof[x] = (float)adc;
|
|
// Serial.printf("%02x ", (unsigned char)adc);
|
|
AFSK_adc_isr(AFSK_modem, adc); // Process signal IIR
|
|
if (x % 4 == 0)
|
|
APRS_poll(); // Poll check every 1 byte
|
|
}
|
|
APRS_poll();
|
|
}
|
|
#endif
|
|
}
|
|
}
|