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Adding V/D type 2 VCH reconstruction (currently disabled). 

I didn't have the chance to test this yet, hence the WRITE_BIT line
is commented out still. It's only a matter of getting the inter-
leaving right now, though.
This commit is contained in:
Mathias Weyland 2016-04-20 13:03:54 +02:00
parent 38760db121
commit 3fa480b047
1 changed files with 16 additions and 0 deletions
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16
YSFPayload.cpp
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@ -405,6 +405,22 @@ void CYSFPayload::decodeVDMode2(unsigned char fn)
errors++; errors++;
} }
} }
// Reconstruct only if we have bit errors. Technically we could even
// constrain it individually to the 5 VCH sections.
if(errors)
{
// Scramble
for (unsigned int i = 0U; i < 13U; i++)
vch[i] ^= WHITENING_DATA[i];
// Interleave
for(unsigned int i = 0U; i < 104U; i++) {
unsigned int n = INTERLEAVE_TABLE_26_4[i];
bool s = READ_BIT1(m_data, i);
//WRITE_BIT1(m_data, offset+n, s);
}
}
} }
LogMessage("YSF, V/D Mode 2, Repetition FEC %u/270 (%.1f%%)", errors, float(errors) / 270.0F); LogMessage("YSF, V/D Mode 2, Repetition FEC %u/270 (%.1f%%)", errors, float(errors) / 270.0F);