Fix DSP output for DMR SB/RC;

Fix DSP output order on BS voice loop;
RC PDU Format Line Break;
Debug RC data testing on BS VC-F;

src/dmr_bs.c

@@ -200,13 +200,13 @@ void dmrBS (dsd_opts * opts, dsd_state * state)
     syncdata[(2*i)+1] = (1 & dibit);         // bit 0
 
     //embedded link control
-    if(internalslot == 0 && vc1 > 1 && vc1 < 7) //grab on vc1 values 2-5 B C D and E
+    if(internalslot == 0 && vc1 > 1 && vc1 < 7) //grab on vc1 values 2-5 B C D E, and F
     {
       state->dmr_embedded_signalling[internalslot][vc1-1][i*2]   = (1 & (dibit >> 1)); // bit 1
       state->dmr_embedded_signalling[internalslot][vc1-1][i*2+1] = (1 & dibit); // bit 0
     }
 
-    if(internalslot == 1 && vc2 > 1 && vc2 < 7) //grab on vc2 values 2-5 B C D and E
+    if(internalslot == 1 && vc2 > 1 && vc2 < 7) //grab on vc2 values 2-5 B C D E, and F
     {
       state->dmr_embedded_signalling[internalslot][vc2-1][i*2]   = (1 & (dibit >> 1)); // bit 1
       state->dmr_embedded_signalling[internalslot][vc2-1][i*2+1] = (1 & dibit); // bit 0
@@ -299,6 +299,40 @@ void dmrBS (dsd_opts * opts, dsd_state * state)
     goto SKIP;
   }
 
+  //ETSI TS 102 361-1 V2.6.1 Table E.2 and E.4
+  //check for a rc burst with bptc or 34 rate data in it (testing only)
+  // #define RC_TESTING //disable if not in use
+  #ifdef RC_TESTING
+  if ( (strcmp (sync, DMR_BS_DATA_SYNC) != 0) && (strcmp (sync, DMR_BS_VOICE_SYNC) != 0) && 
+       ( (internalslot == 0 && vc1 == 6) ||  (internalslot == 1 && vc2 == 6) )              )
+  {
+
+    //if the QR FEC is good, and the P/PI bit is on for RC
+    if (QR_16_7_6_decode(emb_pdu) && emb_pdu[4])
+    {
+      fprintf (stderr,"%s ", timestr);
+
+      if (opts->inverted_dmr == 0)
+        fprintf (stderr,"Sync: +RC   ");
+      else fprintf (stderr,"Sync: -RC   ");
+
+      dmr_data_sync (opts, state);
+
+      dmr_data_burst_handler(opts, state, (uint8_t *)dummy_bits, 0xEB);
+
+      dmr_sbrc (opts, state, emb_pdu[4]);
+
+      if (internalslot == 0)
+        vc1 = 7;
+      else vc2 = 7;
+
+      goto SKIP;
+
+    }
+
+  }
+  #endif //RC_TESTING
+
   //check to see if we are expecting a VC at this point vc > 7
   if (strcmp (sync, DMR_BS_DATA_SYNC) != 0 && internalslot == 0 && vc1 > 6)
   {
@@ -463,7 +497,27 @@ void dmrBS (dsd_opts * opts, dsd_state * state)
       memcpy(state->s_r4[2], state->s_r, sizeof(state->s_r));
       memcpy(state->s_r4u[2], state->s_ru, sizeof(state->s_ru));
     }
-      
+
+
+    //'DSP' output to file -- run before sbrc
+    if (opts->use_dsp_output == 1)
+    {
+      FILE * pFile; //file pointer
+      pFile = fopen (opts->dsp_out_file, "a");
+      fprintf (pFile, "\n%d 98 ", internalslot+1); //'98' is CACH designation value
+      for (i = 0; i < 6; i++) //3 byte CACH
+      {
+        int cach_byte = (state->dmr_stereo_payload[i*2] << 2) | state->dmr_stereo_payload[i*2 + 1];
+        fprintf (pFile, "%X", cach_byte);
+      }
+      fprintf (pFile, "\n%d 10 ", internalslot+1); //0x10 for voice burst
+      for (i = 6; i < 72; i++) //33 bytes, no CACH
+      {
+        int dsp_byte = (state->dmr_stereo_payload[i*2] << 2) | state->dmr_stereo_payload[i*2 + 1];
+        fprintf (pFile, "%X", dsp_byte);
+      }
+      fclose (pFile);
+    }
 
     //run sbrc here to look for the late entry key and alg after we observe potential errors in VC6
     if (internalslot == 0 && vc1 == 6) dmr_sbrc (opts, state, power);
@@ -489,26 +543,6 @@ void dmrBS (dsd_opts * opts, dsd_state * state)
       state->last_cc_sync_time = time(NULL);
     }
 
-    //'DSP' output to file
-    if (opts->use_dsp_output == 1)
-    {
-      FILE * pFile; //file pointer
-      pFile = fopen (opts->dsp_out_file, "a");
-      fprintf (pFile, "\n%d 98 ", internalslot+1); //'98' is CACH designation value
-      for (i = 0; i < 6; i++) //3 byte CACH
-      {
-        int cach_byte = (state->dmr_stereo_payload[i*2] << 2) | state->dmr_stereo_payload[i*2 + 1];
-        fprintf (pFile, "%X", cach_byte);
-      }
-      fprintf (pFile, "\n%d 10 ", internalslot+1); //0x10 for voice burst
-      for (i = 6; i < 72; i++) //33 bytes, no CACH
-      {
-        int dsp_byte = (state->dmr_stereo_payload[i*2] << 2) | state->dmr_stereo_payload[i*2 + 1];
-        fprintf (pFile, "%X", dsp_byte);
-      }
-      fclose (pFile);
-    } 
-
     //reset err checks
     cach_err = 1;
     tact_okay = 0;

src/dmr_le.c

@@ -344,6 +344,7 @@ void dmr_sbrc (dsd_opts * opts, dsd_state * state, uint8_t power)
         else if (sbrc_hex == 5) fprintf (stderr, " RC: Cease Transmission Request;");
         else                    fprintf (stderr, " RC: Reserved %02X;", sbrc_hex);
         fprintf (stderr, "%s", KNRM);
+        if (opts->payload == 1) fprintf (stderr, "\n");
       }
 
       //if the call is interruptable (TXI) and the crc3 is okay and TXI Opcode
@@ -427,21 +428,20 @@ void dmr_sbrc (dsd_opts * opts, dsd_state * state, uint8_t power)
 
   SBRC_END:
 
-  //'DSP' output to file -- only RC, or RC and SB?
+  //'DSP' output to file -- SB and RC
-  if (power == 1 && opts->use_dsp_output == 1 && sbrc_hex != 0) //if not NULL
+  if (opts->use_dsp_output == 1)
   {
     FILE * pFile; //file pointer
     pFile = fopen (opts->dsp_out_file, "a");
-    fprintf (pFile, "\n%d 99 ", slot+1); //'99' is RC designation value
+    fprintf (pFile, "\n%d 99 ", slot+1); //'99' is SB and RC designation value
-    int k = 0;
+    for (i = 0; i < 12; i++) //48 bits (includes CC, PPI, LCSS, and QR)
-    for (i = 0; i < 24; i++) //12 bytes, SB or RC
+    // for (i = 2; i < 10; i++) //32 bits (only SB/RC Data and its PC/H)
     {
-      //check to see if k++ starts at zero, or at 1
+      uint8_t sbrc_nib = (state->dmr_embedded_signalling[slot][5][(i*4)+0] << 3) | (state->dmr_embedded_signalling[slot][5][(i*4)+1] << 2) | (state->dmr_embedded_signalling[slot][5][(i*4)+2] << 1) | (state->dmr_embedded_signalling[slot][5][(i*4)+3] << 0);
-      int sbrc_nib = (state->dmr_embedded_signalling[slot][5][k++] << 3) | (state->dmr_embedded_signalling[slot][5][k++] << 2) | (state->dmr_embedded_signalling[slot][5][k++] << 1) | (state->dmr_embedded_signalling[slot][5][k++] << 0);
       fprintf (pFile, "%X", sbrc_nib);
     }
     fclose (pFile);
-  } 
+  }
 
 }
 

src/dmr_ms.c

@@ -157,7 +157,7 @@ void dmrMS (dsd_opts * opts, dsd_state * state)
     syncdata[(2*i)+1] = (1 & dibit);         // bit 0
 
     // load the superframe to do embedded signal processing
-    if(vc > 1) //grab on vc1 values 2-5 B C D and E
+    if(vc > 1) //grab on vc2 values 2-5 B C D E, and F
     {
       state->dmr_embedded_signalling[internalslot][vc-1][i*2]   = (1 & (dibit >> 1)); // bit 1
       state->dmr_embedded_signalling[internalslot][vc-1][i*2+1] = (1 & dibit); // bit 0