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dsd-fme_18_05_2023
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DMR CACH and Burst ERR Tweaking;

This commit is contained in:
lwvmobile 2022-10-17 21:07:58 -04:00
parent 4138f92917
commit 9b92855b4e
5 changed files with 100 additions and 31 deletions
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83
src/dmr_bs.c
View File

@ -26,6 +26,7 @@ void dmrBS (dsd_opts * opts, dsd_state * state)
char redundancyB[36];
unsigned short int vc1;
unsigned short int vc2;
int cach_okay = 0;
//cach fec
char cachdata[25] = {0}; //increased from 24 to 25 to see if this fixes ubuntu 32 bug
@ -76,10 +77,8 @@ void dmrBS (dsd_opts * opts, dsd_state * state)
cachdata[cachInterleave[(i*2)+1]] = (1 & dibit); // bit 0
}
cachdata[25] = 0; //setting to see if this fixes ubuntu 32 bit bug
//decode and correct cach and compare
int cach_okay = 69;
cach_okay = 69;
if ( Hamming_7_4_decode (cachdata) ) //see if we need to de-interleave this...probably do.
{
cach_okay = 1;
@ -91,6 +90,11 @@ void dmrBS (dsd_opts * opts, dsd_state * state)
if (cach_okay != 1)
{
//fprintf (stderr, "CACH FEC Error %d", cach_okay);
if (opts->aggressive_framesync == 1)
{
goto END;
}
}
state->currentslot = cachdata[1];
@ -353,7 +357,7 @@ void dmrBS (dsd_opts * opts, dsd_state * state)
}
//extra check to see if we have missed a voice/data frame sync at this point and then exit if required
if (opts->aggressive_framesync == 1)
if (1 == 1) //opts->aggressive_framesync
{
//extremely aggressive
if ( vc1 > 7 || vc2 > 7 )
@ -541,7 +545,7 @@ void dmrBS (dsd_opts * opts, dsd_state * state)
state->DMRvcR = 0;
if (state->payload_algidR >= 0x21)
{
if (state->payload_miR != 0 && state->payload_algidR == 0x21)
if (state->payload_miR != 0 && state->payload_algidR >= 0x21)
{
LFSR(state);
}
@ -596,9 +600,23 @@ void dmrBS (dsd_opts * opts, dsd_state * state)
state->dmr_stereo = 0;
state->errs2R = 0;
state->errs2 = 0;
//
//
//if we have a cach err, then produce sync pattern/err message
if (cach_okay != 1)
{
fprintf (stderr,"%s ", getTime());
fprintf (stderr,"Sync: DMR ");
fprintf (stderr, "%s", KRED);
fprintf (stderr, "| ** VOICE CACH ERR ** ");
fprintf (stderr, "%s", KNRM);
//run LFSR if either slot had an active MI in it.
state->currentslot = 0;
if (state->payload_algid >= 0x21) LFSR(state);
state->currentslot = 1;
if (state->payload_algidR >= 0x21) LFSR(state);
fprintf (stderr, "\n");
}
}
//Process buffered half frame and 2nd half and then jump to full BS decoding
@ -612,13 +630,16 @@ void dmrBSBootstrap (dsd_opts * opts, dsd_state * state)
const int *w, *x, *y, *z;
char sync[25];
char syncdata[48];
char cachdata[13] = {0};
int mutecurrentslot;
int msMode;
char cc[4];
unsigned char EmbeddedSignalling[16];
unsigned int EmbeddedSignallingOk;
//cach fec
char cachdata[25] = {0}; //increased from 24 to 25 to see if this fixes ubuntu 32 bug
int cachInterleave[24] = {0, 7, 8, 9, 1, 10, 11, 12, 2, 13, 14, 15, 3, 16, 4, 17, 18, 19, 5, 20, 21, 22, 6, 23};
//add time to mirror printFrameSync
time_t now;
char * getTime(void) //get pretty hh:mm:ss timestamp
@ -638,7 +659,6 @@ void dmrBSBootstrap (dsd_opts * opts, dsd_state * state)
//payload buffer
//CACH + First Half Payload + Sync = 12 + 54 + 24
//dibit_p = state->dibit_buf_p - 90; //this seems to work okay for both
dibit_p = state->dmr_payload_p - 90;
for (i = 0; i < 90; i++) //90
{
@ -654,13 +674,32 @@ void dmrBSBootstrap (dsd_opts * opts, dsd_state * state)
for(i = 0; i < 12; i++)
{
dibit = state->dmr_stereo_payload[i];
cachdata[i] = dibit;
if(i == 2)
{
state->currentslot = (1 & (dibit >> 1));
}
cachdata[cachInterleave[(i*2)]] = (1 & (dibit >> 1)); // bit 1
cachdata[cachInterleave[(i*2)+1]] = (1 & dibit); // bit 0
}
//decode and correct cach and compare
int cach_okay = 69;
if ( Hamming_7_4_decode (cachdata) ) //see if we need to de-interleave this...probably do.
{
cach_okay = 1;
}
if (cach_okay == 1)
{
//fprintf (stderr, "CACH Okay ");
}
if (cach_okay != 1)
{
//fprintf (stderr, "CACH FEC Error %d", cach_okay);
if (opts->aggressive_framesync == 1)
{
goto END;
}
}
state->currentslot = cachdata[1];
//Setup for first AMBE Frame
//Interleave Schedule
@ -831,10 +870,20 @@ void dmrBSBootstrap (dsd_opts * opts, dsd_state * state)
processMbeFrame (opts, state, NULL, ambe_fr3, NULL);
dmrBS (opts, state); //bootstrap into full TDMA frame for BS mode
END:
//placing this below to fix compiler error, it will never run but compiler needs something there
if (0 == 1)
//if we have a cach err, then produce sync pattern/err message
if (cach_okay != 1)
{
fprintf (stderr, "this is a dumb thing to have to fix");
fprintf (stderr,"%s ", getTime());
fprintf (stderr,"Sync: DMR ");
fprintf (stderr, "%s", KRED);
fprintf (stderr, "| ** VOICE CACH ERR ** ");
fprintf (stderr, "%s", KNRM);
//run LFSR if either slot had an active MI in it.
state->currentslot = 0;
if (state->payload_algid >= 0x21) LFSR(state);
state->currentslot = 1;
if (state->payload_algidR >= 0x21) LFSR(state);
fprintf (stderr, "\n");
}
}

23
src/dmr_data.c
View File

@ -65,8 +65,6 @@ processDMRdata (dsd_opts * opts, dsd_state * state)
}
cachdata[25] = 0;
//decode and correct cach and compare
int cach_okay = 69;
if ( Hamming_7_4_decode (cachdata) ) //is now de-interleaved appropriately
@ -80,10 +78,14 @@ processDMRdata (dsd_opts * opts, dsd_state * state)
if (cach_okay != 1)
{
//fprintf (stderr, "CACH FEC Error %d", cach_okay);
goto END;
if (opts->aggressive_framesync == 1) //may not worry about it on data
{
goto END;
}
}
state->currentslot = cachdata[1]; //still bit 2, or somewhere else? is it 8? 1? TC?
state->currentslot = cachdata[1];
if (state->currentslot == 0 && state->dmr_ms_mode == 0)
{
@ -306,8 +308,13 @@ processDMRdata (dsd_opts * opts, dsd_state * state)
}
else
{
SlotTypeOk = 0;
goto END;
if (opts->aggressive_framesync == 1)
{
SlotTypeOk = 0;
goto END;
}
}
/* Slot Type parity checked => Fill the color code */
@ -546,10 +553,10 @@ processDMRdata (dsd_opts * opts, dsd_state * state)
fprintf(stderr, "\n");
}
END:
if (SlotTypeOk == 0 || cach_okay == 0)
if (SlotTypeOk == 0 || cach_okay != 1)
{
fprintf (stderr, "%s", KRED);
fprintf (stderr, "| **CACH or Burst Type FEC ERR ** ");
fprintf (stderr, "| ** CACH or Burst Type FEC ERR ** ");
fprintf (stderr, "%s", KNRM);
fprintf (stderr, "\n");
}

7
src/dmr_ms.c
View File

@ -882,7 +882,10 @@ void dmrMSData (dsd_opts * opts, dsd_state * state)
else
{
//fprintf (stderr, "CACH ERR ");
goto END;
if (opts->aggressive_framesync == 1) //may not worry about it on data
{
goto END;
}
}
int slot_okay = -1;
@ -914,7 +917,7 @@ void dmrMSData (dsd_opts * opts, dsd_state * state)
if (slot_okay != 1 || cach_okay != 1)
{
fprintf (stderr, "%s", KRED);
fprintf (stderr, "| **CACH or Burst Type FEC ERR ** ");
fprintf (stderr, "| ** CACH or Burst Type FEC ERR ** ");
fprintf (stderr, "%s", KNRM);
fprintf (stderr, "\n");
}

6
src/dmr_sync.c
View File

@ -2330,7 +2330,7 @@ void ProcessDmrTerminaisonLC(dsd_opts * opts, dsd_state * state, uint8_t info[19
fprintf (stderr, "%s \n", KRED);
fprintf (stderr, " SLOT %d ", state->currentslot+1);
fprintf(stderr, "TGT=%u SRC=%u ", TSVoiceSupFrame->FullLC.GroupAddress, TSVoiceSupFrame->FullLC.SourceAddress);
fprintf(stderr, "FID=0x%02X SVC=0x%02X", TSVoiceSupFrame->FullLC.FeatureSetID, TSVoiceSupFrame->FullLC.ServiceOptions);
fprintf(stderr, "FID=0x%02X SVC=0x%02X ", TSVoiceSupFrame->FullLC.FeatureSetID, TSVoiceSupFrame->FullLC.ServiceOptions);
fprintf (stderr, "%s ", KNRM);
}
@ -2339,8 +2339,8 @@ void ProcessDmrTerminaisonLC(dsd_opts * opts, dsd_state * state, uint8_t info[19
fprintf (stderr, "%s \n", KRED);
fprintf (stderr, " SLOT %d ", state->currentslot+1);
fprintf(stderr, "TGT=%u SRC=%u ", TSVoiceSupFrame->FullLC.GroupAddress, TSVoiceSupFrame->FullLC.SourceAddress);
fprintf(stderr, "FID=0x%02X SVC=0x%02X", TSVoiceSupFrame->FullLC.FeatureSetID, TSVoiceSupFrame->FullLC.ServiceOptions);
fprintf(stderr, "RAS (FEC OK/CRC ERR)"); //tlc
fprintf(stderr, "FID=0x%02X SVC=0x%02X ", TSVoiceSupFrame->FullLC.FeatureSetID, TSVoiceSupFrame->FullLC.ServiceOptions);
fprintf(stderr, "RAS (FEC OK/CRC ERR) "); //tlc
fprintf (stderr, "%s ", KNRM);
}

12
src/fec.c
View File

@ -330,6 +330,7 @@ bool Hamming_7_4_decode(unsigned char *rxBits) // corrects in place
{
unsigned int syndromeI = 0; // syndrome index
int is = 0;
int correction = 0;
for (is = 0; is < 3; is++)
{
@ -351,6 +352,13 @@ bool Hamming_7_4_decode(unsigned char *rxBits) // corrects in place
else
{
rxBits[Hamming_7_4_m_corr[syndromeI]] ^= 1; // flip bit
correction++;
}
//not sure of upper limit on what hamming can correct (if any),
//but will test with 0 and 1 to see how those perform
if (correction > 1)
{
return false;
}
}
@ -926,8 +934,10 @@ bool Golay_20_8_decode(unsigned char *rxBits)
{
return false;
}
//return false due to exceeding the number of allowed corrected bits
//being stingy and only allowing 1 error, may wreck some good data decodes,
//decided to play it safe with 2
if (correction > 2)
{
return false;