Tweak RAS/CRC; Other Misc Tweaks;
This commit is contained in:
parent
485161f42d
commit
d2d750e920
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@ -3,5 +3,6 @@
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*.dylib
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*.dylib
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build
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build
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*.sh
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*.sh
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*.csv
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examples
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@ -210,8 +210,6 @@ void dmr_data_burst_handler(dsd_opts * opts, dsd_state * state, uint8_t info[196
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//debug print
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//debug print
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//fprintf (stderr, " RAS? %X - %d %d %d", BPTCReservedBits, R[0], R[1], R[2]);
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//fprintf (stderr, " RAS? %X - %d %d %d", BPTCReservedBits, R[0], R[1], R[2]);
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//set the 'RAS Flag'
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if (BPTCReservedBits != 0) is_ras = 1; //!=0, or == 0x4
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/* Convert the 96 bits BPTC data into 12 bytes */
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/* Convert the 96 bits BPTC data into 12 bytes */
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k = 0;
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k = 0;
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@ -252,7 +250,17 @@ void dmr_data_burst_handler(dsd_opts * opts, dsd_state * state, uint8_t info[196
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CRCComputed = ComputeCrcCCITT(BPTCDmrDataBit);
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CRCComputed = ComputeCrcCCITT(BPTCDmrDataBit);
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if (CRCComputed == CRCExtracted) CRCCorrect = 1;
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if (CRCComputed == CRCExtracted) CRCCorrect = 1;
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else CRCCorrect = 0;
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else CRCCorrect = 0;
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}
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}
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//set the 'RAS Flag', if no irrecoverable errors but bad crc
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if (CRCCorrect == 0 && IrrecoverableErrors == 0 && BPTCReservedBits == 4) is_ras = 1; //!=0, or == 0x4, or just R[2] == 1
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//make sure the system type isn't Hytera, but could just be bad decodes on bad sample
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if (BPTCDmrDataByte[1] == 0x68) is_ras = 0;
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//if this is a RAS system, set the CRC to okay if irrecoverable errors is okay
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//if we don't do this, then we can't view some data (CSBKs on RAS enabled systems)
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if (is_ras == 1) CRCCorrect = 1;
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if (databurst == 0x04 || databurst == 0x06) //MBC Header, Data Header
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if (databurst == 0x04 || databurst == 0x06) //MBC Header, Data Header
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{
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{
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@ -444,10 +452,11 @@ void dmr_data_burst_handler(dsd_opts * opts, dsd_state * state, uint8_t info[196
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if (databurst == 0x05) dmr_block_assembler (opts, state, DMR_PDU, pdu_len, databurst, 2);
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if (databurst == 0x05) dmr_block_assembler (opts, state, DMR_PDU, pdu_len, databurst, 2);
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//print whether or not the 'RAS Field' bits are set to indicate RAS enabled (to be verified)
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//print whether or not the 'RAS Field' bits are set to indicate RAS enabled (to be verified)
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if (IrrecoverableErrors == 0 && is_ras == 1)
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if (is_ras == 1)
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{
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{
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fprintf (stderr, "%s", KRED);
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fprintf (stderr, "%s", KRED);
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fprintf (stderr, " RAS ");
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fprintf (stderr, " CRC/RAS ");
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//the value of this field seems to always, or usually, be 4, or just R[2] bit is set
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if (opts->payload == 1) fprintf (stderr, "%X ", BPTCReservedBits);
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if (opts->payload == 1) fprintf (stderr, "%X ", BPTCReservedBits);
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fprintf (stderr, "%s", KNRM);
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fprintf (stderr, "%s", KNRM);
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}
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}
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@ -53,7 +53,7 @@ void dmr_flco (dsd_opts * opts, dsd_state * state, uint8_t lc_bits[], uint32_t C
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}
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}
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if (IrrecoverableErrors == 0)
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if (IrrecoverableErrors == 0 && CRCCorrect == 1)
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{
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{
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//Embedded Talker Alias Header Only (format and len storage)
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//Embedded Talker Alias Header Only (format and len storage)
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if (type == 3 && flco == 0x04)
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if (type == 3 && flco == 0x04)
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@ -90,7 +90,7 @@ void dmr_flco (dsd_opts * opts, dsd_state * state, uint8_t lc_bits[], uint32_t C
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//will want to continue to observe for different flco and fid combinations to find out their meaning
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//will want to continue to observe for different flco and fid combinations to find out their meaning
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//Standard Addressing/Cap+ Addressing (trying to avoid embedded alias and gps, etc)
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//Standard Addressing/Cap+ Addressing (trying to avoid embedded alias and gps, etc)
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if(IrrecoverableErrors == 0 && is_alias == 0 && is_gps == 0)
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if(IrrecoverableErrors == 0 && is_alias == 0 && is_gps == 0 && CRCCorrect == 1)
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{
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{
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//set overarching manufacturer in use when non-standard feature id set is up
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//set overarching manufacturer in use when non-standard feature id set is up
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//may not want to set moto 0x10 here either, lots of radios use that set as well
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//may not want to set moto 0x10 here either, lots of radios use that set as well
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114
src/dmr_le.c
114
src/dmr_le.c
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@ -183,26 +183,29 @@ void dmr_sbrc (dsd_opts * opts, dsd_state * state, uint8_t power)
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if (opts->payload == 1) fprintf (stderr, " CRC EXT %02X, CRC CMP %02X", crc_extracted, crc_computed);
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if (opts->payload == 1) fprintf (stderr, " CRC EXT %02X, CRC CMP %02X", crc_extracted, crc_computed);
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}
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}
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else crc_okay = 1; //SB
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else crc_okay = 1; //SB
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fprintf (stderr, "\n %s", KCYN);
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if (power == 0) fprintf (stderr, " SB: ");
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if (power == 1) fprintf (stderr, " RC: ");
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for(i = 0; i < 11; i++)
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{
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sbrc_hex = sbrc_hex << 1;
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sbrc_hex |= sbrc_return[i] & 1; //sbrc_return
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fprintf (stderr, "%d", sbrc_return[i]);
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}
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fprintf (stderr, " - %03X", sbrc_hex);
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fprintf (stderr, "%s", KNRM);
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if (crc_okay == 0)
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if (opts->payload == 1) //hide the sb/rc behind the payload printer, won't be useful to most people right now
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{
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{
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fprintf (stderr, "%s", KRED);
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fprintf (stderr, "\n %s", KCYN);
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fprintf (stderr, " (CRC ERR)");
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if (power == 0) fprintf (stderr, " SB: ");
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if (power == 1) fprintf (stderr, " RC: ");
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for(i = 0; i < 11; i++)
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{
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sbrc_hex = sbrc_hex << 1;
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sbrc_hex |= sbrc_return[i] & 1; //sbrc_return
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fprintf (stderr, "%d", sbrc_return[i]);
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}
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fprintf (stderr, " - %03X", sbrc_hex);
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fprintf (stderr, "%s", KNRM);
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fprintf (stderr, "%s", KNRM);
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}
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if (crc_okay == 0)
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{
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fprintf (stderr, "%s", KRED);
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fprintf (stderr, " (CRC ERR)");
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fprintf (stderr, "%s", KNRM);
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}
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}
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//sbrc_hex value of 0x313 seems to be some Cap+ Thing,
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//sbrc_hex value of 0x313 seems to be some Cap+ Thing,
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//also observed 0x643 on another cap+ system (site id, status? something?)
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//also observed 0x643 on another cap+ system (site id, status? something?)
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//I've observed it in the Private Cap+ TXI calls as well
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//I've observed it in the Private Cap+ TXI calls as well
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@ -211,58 +214,61 @@ void dmr_sbrc (dsd_opts * opts, dsd_state * state, uint8_t power)
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uint8_t alg = sbrc_hex & 3;
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uint8_t alg = sbrc_hex & 3;
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uint16_t key = (sbrc_hex >> 3) & 0xFF;
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uint16_t key = (sbrc_hex >> 3) & 0xFF;
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if (irr_err != 0) fprintf (stderr, "%s (FEC ERR) %d %s", KRED, irr_err, KNRM);
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if (opts->payload == 1)
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if (irr_err == 0)
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{
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{
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if (sbrc_hex == 0) ; //NULL
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if (irr_err != 0) fprintf (stderr, "%s (FEC ERR) %d %s", KRED, irr_err, KNRM);
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else if (sbrc_hex == 0x313)
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if (irr_err == 0)
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{
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//Cap+ Thing? Observed On Cap+ Systems
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// fprintf (stderr, " Cap+ Thing?");
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}
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else
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{
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{
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if (sbrc_hex == 0) ; //NULL
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else if (sbrc_hex == 0x313)
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{
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//Cap+ Thing? Observed On Cap+ Systems
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// fprintf (stderr, " Cap+ Thing?");
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}
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else
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{
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if (slot == 0)
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if (slot == 0)
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{
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//key and alg only present SOME times, not all,
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//also, intermixed with other signalling
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//needs more study first!
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if (state->dmr_so & 0x40 && key != 0 && state->payload_keyid == 0)
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{
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{
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if (opts->payload == 1)
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//key and alg only present SOME times, not all,
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//also, intermixed with other signalling
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//needs more study first!
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if (state->dmr_so & 0x40 && key != 0 && state->payload_keyid == 0)
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{
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{
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fprintf (stderr, "%s ", KYEL);
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if (opts->payload == 1)
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fprintf (stderr, "\n Slot 1");
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{
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fprintf (stderr, " DMR LE SB ALG ID: %X KEY ID: %0X", alg + 0x20, key);
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fprintf (stderr, "%s ", KYEL);
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fprintf (stderr, "%s ", KNRM);
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fprintf (stderr, "\n Slot 1");
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fprintf (stderr, " DMR LE SB ALG ID: %X KEY ID: %0X", alg + 0x20, key);
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fprintf (stderr, "%s ", KNRM);
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}
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//needs more study before assignment
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//state->payload_keyid = key;
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//state->payload_algid = alg + 0x20; //assuming DMRA approved alg values (moto patent)
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}
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}
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//needs more study before assignment
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//state->payload_keyid = key;
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//state->payload_algid = alg + 0x20; //assuming DMRA approved alg values (moto patent)
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}
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}
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}
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if (slot == 1)
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if (slot == 1)
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{
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if (state->dmr_soR & 0x40 && key != 0 && state->payload_keyidR == 0)
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{
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{
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if (opts->payload == 1)
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if (state->dmr_soR & 0x40 && key != 0 && state->payload_keyidR == 0)
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{
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{
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fprintf (stderr, "%s ", KYEL);
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if (opts->payload == 1)
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fprintf (stderr, "\n Slot 2");
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{
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fprintf (stderr, " DMR LE SB ALG ID: %X KEY ID: %0X", alg + 0x20, key);
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fprintf (stderr, "%s ", KYEL);
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fprintf (stderr, "%s ", KNRM);
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fprintf (stderr, "\n Slot 2");
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fprintf (stderr, " DMR LE SB ALG ID: %X KEY ID: %0X", alg + 0x20, key);
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fprintf (stderr, "%s ", KNRM);
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}
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//needs more study before assignment
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//state->payload_keyidR = key;
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//state->payload_algidR = alg + 0x20; //assuming DMRA approved alg values (moto patent)
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}
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}
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//needs more study before assignment
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//state->payload_keyidR = key;
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//state->payload_algidR = alg + 0x20; //assuming DMRA approved alg values (moto patent)
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}
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}
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}
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}
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}
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}
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}
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}
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SBRC_END:
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SBRC_END:
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@ -33,11 +33,11 @@ processProVoice (dsd_opts * opts, dsd_state * state)
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#ifdef PROVOICE_DUMP
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#ifdef PROVOICE_DUMP
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fprintf (stderr," ");
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fprintf (stderr," ");
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#endif
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#endif
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//init Bits (64)...MI?
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//iNitial 64 bits
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if (opts->payload == 1)
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if (opts->payload == 1)
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{
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{
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k = 0;
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k = 0;
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//fprintf (stderr, "\nInit 64 ");
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fprintf (stderr, "\n N64: ");
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for(i = 0; i < 8; i++)
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for(i = 0; i < 8; i++)
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{
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{
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initbyte[i] = 0;
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initbyte[i] = 0;
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@ -47,9 +47,10 @@ processProVoice (dsd_opts * opts, dsd_state * state)
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initbyte[i] = initbyte[i] | init[k];
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initbyte[i] = initbyte[i] | init[k];
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k++;
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k++;
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}
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}
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//fprintf (stderr, "%02X", initbyte[i]);
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fprintf (stderr, "%02X", initbyte[i]);
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if (i == 3) fprintf (stderr, "-");
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}
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}
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//fprintf (stderr, "\n");
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fprintf (stderr, "\n");
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}
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}
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// lid
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// lid
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for (i = 0; i < 16; i++)
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for (i = 0; i < 16; i++)
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@ -79,7 +80,7 @@ processProVoice (dsd_opts * opts, dsd_state * state)
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if (opts->payload == 1)
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if (opts->payload == 1)
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{
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{
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k = 0;
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k = 0;
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//fprintf (stderr, "LID ");
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fprintf (stderr, " LID: ");
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for(i = 0; i < 10; i++)
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for(i = 0; i < 10; i++)
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{
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{
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lidbyte[i] = 0;
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lidbyte[i] = 0;
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@ -89,9 +90,10 @@ processProVoice (dsd_opts * opts, dsd_state * state)
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lidbyte[i] = lidbyte[i] | lid[k];
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lidbyte[i] = lidbyte[i] | lid[k];
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k++;
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k++;
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}
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}
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//fprintf (stderr, "%02X", lidbyte[i]);
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fprintf (stderr, "%02X", lidbyte[i]);
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if (i == 3 || i == 7) fprintf (stderr, "-");
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}
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}
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//fprintf (stderr, "\n");
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// fprintf (stderr, "\n");
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}
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}
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@ -337,7 +339,7 @@ processProVoice (dsd_opts * opts, dsd_state * state)
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if (opts->payload == 1)
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if (opts->payload == 1)
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{
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{
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k = 0;
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k = 0;
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//fprintf (stderr, "16 bits? ");
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fprintf (stderr, "\n 16B: ");
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for(i = 0; i < 2; i++)
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for(i = 0; i < 2; i++)
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{
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{
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initbyte[i] = 0;
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initbyte[i] = 0;
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@ -347,9 +349,9 @@ if (opts->payload == 1)
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initbyte[i] = initbyte[i] | init[k];
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initbyte[i] = initbyte[i] | init[k];
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k++;
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k++;
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}
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}
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//fprintf (stderr, "%02X", initbyte[i]);
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fprintf (stderr, "%02X", initbyte[i]);
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}
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}
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//fprintf (stderr, "\n");
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// fprintf (stderr, "\n");
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}
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}
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// imbe frames 3,4 first half
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// imbe frames 3,4 first half
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w = pW;
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w = pW;
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