673 lines
18 KiB
C
673 lines
18 KiB
C
#include "dsd.h"
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#include "dmr_const.h"
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//A subroutine for processing each TDMA frame individually to allow for
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//processing voice and/or data on both BS slots (channels) simultaneously
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void dmrBS (dsd_opts * opts, dsd_state * state)
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{
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int i, j, k, l, dibit;
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int *dibit_p;
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char ambe_fr[4][24] = {0};
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char ambe_fr2[4][24] = {0};
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char ambe_fr3[4][24] = {0};
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char t_ambe_fr[4][24] = {9};
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char t_ambe_fr2[4][24] = {9};
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char t_ambe_fr3[4][24] = {9};
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const int *w, *x, *y, *z;
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char sync[25] = {0};
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char syncdata[48] = {0};
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char cachdata[13] = {0};
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int mutecurrentslot;
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int msMode;
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char cc[4];
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unsigned char EmbeddedSignalling[16] = {0};
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int EmbeddedSignallingOk;
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unsigned int internalcolorcode;
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int internalslot;
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char redundancyA[36];
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char redundancyB[36];
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unsigned short int vc1;
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unsigned short int vc2;
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//add time to mirror printFrameSync
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time_t now;
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char * getTime(void) //get pretty hh:mm:ss timestamp
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{
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time_t t = time(NULL);
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char * curr;
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char * stamp = asctime(localtime( & t));
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curr = strtok(stamp, " ");
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curr = strtok(NULL, " ");
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curr = strtok(NULL, " ");
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curr = strtok(NULL, " ");
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return curr;
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}
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//Init the superframe buffers
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//memset(&state->TS1SuperFrame, 0, sizeof(TimeSlotVoiceSuperFrame_t));
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//memset(&state->TS2SuperFrame, 0, sizeof(TimeSlotVoiceSuperFrame_t));
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//Init slot lights
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sprintf (state->slot1light, " slot1 ");
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sprintf (state->slot2light, " slot2 ");
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//Init the color code status
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state->color_code_ok = 0;
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vc1 = 2;
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vc2 = 2;
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short int loop = 1;
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short int skipcount = 0;
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//Run Loop while the getting is good
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while (loop == 1) {
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// CACH
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internalslot = -1; //reset here so we know if this value is being set properly
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for(i = 0; i < 12; i++)
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{
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dibit = getDibit(opts, state);
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cachdata[i] = dibit;
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state->dmr_stereo_payload[i] = dibit;
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if(i == 2)
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{
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state->currentslot = (1 & (dibit >> 1));
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internalslot = (1 & (dibit >> 1));
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}
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}
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//Setup for first AMBE Frame
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//Interleave Schedule
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w = rW;
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x = rX;
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y = rY;
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z = rZ;
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//First AMBE Frame, Full 36
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for(i = 0; i < 36; i++)
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{
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dibit = getDibit(opts, state);
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state->dmr_stereo_payload[i+12] = dibit;
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redundancyA[i] = dibit;
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ambe_fr[*w][*x] = (1 & (dibit >> 1)); // bit 1
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ambe_fr[*y][*z] = (1 & dibit); // bit 0
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w++;
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x++;
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y++;
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z++;
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}
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//check for repetitive data if caught in a 'no carrier' loop? Just picking random values.
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//this will test for no carrier (input signal) and return us to no sync state if necessary
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if (redundancyA[16] == redundancyB[16] && redundancyA[27] == redundancyB[27] &&
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redundancyA[01] == redundancyB[01] && redundancyA[32] == redundancyB[32] &&
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redundancyA[03] == redundancyB[03] && redundancyA[33] == redundancyB[33] &&
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redundancyA[13] == redundancyB[13] && redundancyA[07] == redundancyB[07] )
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{
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goto END;
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}
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// end redundancy test, set B to A
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for(i = 0; i < 36; i++)
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{
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redundancyB[i] = redundancyA[i];
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}
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//Setup for Second AMBE Frame
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//Interleave Schedule
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w = rW;
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x = rX;
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y = rY;
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z = rZ;
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//Second AMBE Frame, First Half 18 dibits just before Sync or EmbeddedSignalling
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for(i = 0; i < 18; i++)
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{
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dibit = getDibit(opts, state);
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state->dmr_stereo_payload[i+48] = dibit;
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ambe_fr2[*w][*x] = (1 & (dibit >> 1)); // bit 1
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ambe_fr2[*y][*z] = (1 & dibit); // bit 0
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w++;
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x++;
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y++;
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z++;
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}
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//short int l = 0; //do I still use this?
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// signaling data or sync
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for(i = 0; i < 24; i++)
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{
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dibit = getDibit(opts, state);
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state->dmr_stereo_payload[i+66] = dibit;
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syncdata[(2*i)] = (1 & (dibit >> 1)); // bit 1
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syncdata[(2*i)+1] = (1 & dibit); // bit 0
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sync[i] = (dibit | 1) + 48;
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if (i < 4 || i > 19) //
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{
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EmbeddedSignalling[2*i] = (1 & (dibit >> 1)); // bit 1
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EmbeddedSignalling[2*i+1] = (1 & dibit); // bit 0
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}
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//Used for ProcessVoiceBurstSync
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if(internalslot == 0 && vc1 > 1 && vc1 < 6) //grab on vc1 values 2-5 B C D and E
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{
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/* Time slot 1 superframe buffer filling => SYNC data */
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state->TS1SuperFrame.TimeSlotRawVoiceFrame[vc1-1].Sync[i*2] = (1 & (dibit >> 1)); // bit 1
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state->TS1SuperFrame.TimeSlotRawVoiceFrame[vc1-1].Sync[i*2+1] = (1 & dibit); // bit 0
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}
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if(internalslot == 1 && vc2 > 1 && vc2 < 6) //grab on vc2 values 2-5 B C D and E
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{
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/* Time slot 2 superframe buffer filling => SYNC data */
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state->TS2SuperFrame.TimeSlotRawVoiceFrame[vc2-1].Sync[i*2] = (1 & (dibit >> 1)); // bit 1
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state->TS2SuperFrame.TimeSlotRawVoiceFrame[vc2-1].Sync[i*2+1] = (1 & dibit); // bit 0
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}
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}
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sync[24] = 0;
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if (internalslot == 0 && vc1 == 6)
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{
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//fprintf (stderr, "\nVC6 Burst = %X\n", syncdata);
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}
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if (internalslot == 1 && vc2 == 6)
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{
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//fprintf (stderr, "\nVC6 Burst = %X\n", syncdata);
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}
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EmbeddedSignallingOk = -1;
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if(QR_16_7_6_decode(EmbeddedSignalling))
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{
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EmbeddedSignallingOk = 1;
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}
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internalcolorcode = 69; //set so we know if this value is being set properly
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if( EmbeddedSignallingOk == 1 ) //don't set on 1?
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{
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//state->color_code = (unsigned int)((EmbeddedSignalling[0] << 3) + (EmbeddedSignalling[1] << 2) + (EmbeddedSignalling[2] << 1) + EmbeddedSignalling[3]);
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internalcolorcode = (unsigned int)((EmbeddedSignalling[0] << 3) + (EmbeddedSignalling[1] << 2) + (EmbeddedSignalling[2] << 1) + EmbeddedSignalling[3]);
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state->color_code_ok = EmbeddedSignallingOk;
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//Power Indicator, not the other PI (header)
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state->PI = (unsigned int)EmbeddedSignalling[4];
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state->PI_ok = EmbeddedSignallingOk;
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//Link Control Start Stop Indicator
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state->LCSS = (unsigned int)((EmbeddedSignalling[5] << 1) + EmbeddedSignalling[6]);
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state->LCSS_ok = EmbeddedSignallingOk;
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}
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else skipcount++;
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//Continue Second AMBE Frame, 18 after Sync or EmbeddedSignalling
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for(i = 0; i < 18; i++)
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{
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dibit = getDibit(opts, state);
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if(opts->inverted_dmr == 1)
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{
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//dibit = (dibit ^ 2);
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}
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state->dmr_stereo_payload[i+90] = dibit;
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ambe_fr2[*w][*x] = (1 & (dibit >> 1)); // bit 1
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ambe_fr2[*y][*z] = (1 & dibit); // bit 0
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w++;
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x++;
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y++;
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z++;
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}
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//Setup for Third AMBE Frame
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//Interleave Schedule
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w = rW;
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x = rX;
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y = rY;
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z = rZ;
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//Third AMBE Frame, Full 36
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for(i = 0; i < 36; i++)
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{
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dibit = getDibit(opts, state);
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if(opts->inverted_dmr == 1)
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{
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//dibit = (dibit ^ 2);
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}
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state->dmr_stereo_payload[i+108] = dibit;
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ambe_fr3[*w][*x] = (1 & (dibit >> 1)); // bit 1
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ambe_fr3[*y][*z] = (1 & dibit); // bit 0
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w++;
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x++;
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y++;
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z++;
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}
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//reset vc counters to 1 if new voice sync frame on each slot
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if ( strcmp (sync, DMR_BS_VOICE_SYNC) == 0)
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{
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if (internalslot == 0)
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{
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vc1 = 1;
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state->dropL = 256;
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}
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if (internalslot == 1)
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{
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vc2 = 1;
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state->dropR = 256;
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}
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}
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//check for sync pattern here after collected the rest of the payload, decide what to do with it
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if ( strcmp (sync, DMR_BS_DATA_SYNC) == 0 )
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{
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fprintf (stderr,"%s ", getTime());
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if (internalslot == 0)
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{
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sprintf(state->slot1light, "[slot1]");
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sprintf(state->slot2light, " slot2 ");
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if (opts->inverted_dmr == 0)
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{
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fprintf (stderr,"Sync: +DMR ");
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}
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else fprintf (stderr,"Sync: -DMR ");
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//constantly reset the vc counter to 1 each data frame in anticipation of new voice frame
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vc1 = 1;
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state->dropL = 256;
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}
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if (internalslot == 1)
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{
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sprintf(state->slot2light, "[slot2]");
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sprintf(state->slot1light, " slot1 ");
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if (opts->inverted_dmr == 0)
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{
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fprintf (stderr,"Sync: +DMR ");
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}
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else fprintf (stderr,"Sync: -DMR ");
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//constantly reset the vc counter to 1 each data frame in anticipation of new voice frame
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vc2 = 1;
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state->dropR = 256;
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}
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processDMRdata (opts, state);
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skipcount++; //after 2 data frames, drop back to getFrameSync and process subsequent data with processDMRdata
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goto SKIP;
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}
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//find way to mitigate or correct coming back here after leaving in inverted signal
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if ( strcmp (sync, DMR_BS_DATA_SYNC) == 0 && opts->inverted_dmr == 1)
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{
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skipcount++;
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goto SKIP;
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}
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//only play voice on no data sync
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if (strcmp (sync, DMR_BS_DATA_SYNC) != 0)
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{
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if (EmbeddedSignallingOk == 0)
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{
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//goto END;
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}
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skipcount = 0; //reset skip count if processing voice frames
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fprintf (stderr,"%s ", getTime());
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if (internalslot == 0)
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{
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state->dmrburstL = 16; //use 16 for Voice?
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//fprintf (stderr,"Sync: +DMR [slot1] slot2 | Color Code=%02d | DMRSTEREO | VC%d \n", state->dmr_color_code, vc1);
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if (opts->inverted_dmr == 0)
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{
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fprintf (stderr,"Sync: +DMR [SLOT1] slot2 | | DMRSTEREO | VC%d ",vc1);
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if (state->K > 0 && state->dmr_so & 0x40 && state->payload_keyid == 0)
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{
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fprintf (stderr, "%s", KYEL);
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fprintf(stderr, " BPK %lld", state->K);
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fprintf (stderr, "%s", KNRM);
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}
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if (vc1 == 1 && state->payload_algid != 0 && opts->payload == 1)
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{
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LFSR(state);
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}
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fprintf (stderr, "\n");
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}
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else
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{
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fprintf (stderr,"Sync: -DMR [SLOT1] slot2 | | DMRSTEREO | VC%d ",vc1);
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if (state->K > 0 && state->dmr_so & 0x40 && state->payload_keyid == 0)
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{
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fprintf (stderr, "%s", KYEL);
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fprintf(stderr, " BPK %lld", state->K);
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fprintf (stderr, "%s", KNRM);
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}
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if (vc1 == 1 && state->payload_algid != 0 && opts->payload == 1)
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{
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LFSR(state);
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}
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fprintf (stderr, "\n");
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}
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}
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if (internalslot == 1)
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{
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state->dmrburstR = 16; //use 16 for Voice?
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if (opts->inverted_dmr == 0)
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{
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fprintf (stderr,"Sync: +DMR slot1 [SLOT2] | | DMRSTEREO | VC%d ",vc2);
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if (state->K > 0 && state->dmr_soR & 0x40 && state->payload_keyidR == 0)
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{
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fprintf (stderr, "%s", KYEL);
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fprintf(stderr, " BPK %lld", state->K);
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fprintf (stderr, "%s", KNRM);
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}
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if (vc2 == 1 && state->payload_algidR != 0 && opts->payload == 1)
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{
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LFSR(state);
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}
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fprintf (stderr, "\n");
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}
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else
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{
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fprintf (stderr,"Sync: -DMR slot1 [SLOT2] | | DMRSTEREO | VC%d ",vc2);
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if (state->K > 0 && state->dmr_soR & 0x40 && state->payload_keyidR == 0)
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{
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fprintf (stderr, "%s", KYEL);
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fprintf(stderr, " BPK %lld", state->K);
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fprintf (stderr, "%s", KNRM);
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}
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if (vc2 == 1 && state->payload_algidR != 0 && opts->payload == 1)
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{
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LFSR(state);
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}
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fprintf (stderr, "\n");
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}
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}
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if (internalslot == 0 && vc1 == 6) //presumably when full (and no sync issues)
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{
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//process voice burst
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ProcessVoiceBurstSync(opts, state);
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fprintf (stderr, "\n");
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}
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if (internalslot == 1 && vc2 == 6) //presumably when full (and no sync issues)
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{
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//process voice burst
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ProcessVoiceBurstSync(opts, state);
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fprintf (stderr, "\n");
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}
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processMbeFrame (opts, state, NULL, ambe_fr, NULL);
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processMbeFrame (opts, state, NULL, ambe_fr2, NULL);
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processMbeFrame (opts, state, NULL, ambe_fr3, NULL);
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if (internalslot == 0)
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{
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vc1++;
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}
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if (internalslot == 1)
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{
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vc2++;
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}
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}
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// recalibrate center/umid/lmid, not sure this helps or does anything particularly in this case
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state->center = ((state->max) + (state->min)) / 2;
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state->umid = (((state->max) - state->center) * 5 / 8) + state->center;
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state->lmid = (((state->min) - state->center) * 5 / 8) + state->center;
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//Escape conditions to break the loop
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//7 seems optimal, allows for an extra frame each in case of late entry on dual voices
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if ( (vc1 > 7 && vc2 > 7) )
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{
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goto END;
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}
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//14 probably allows a few more in case of a bit of jitter but eventually breaks loop (1 second?)
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if ( (vc1 > 14 || vc2 > 14) )
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{
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goto END;
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}
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//using these conditions may cause excessive resyncs IF bad signal,
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//but still better than getting stuck in a wonk wonk loop for too long.
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//set for more aggressive or less aggressive resync during accumulated playback errs
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if (opts->aggressive_framesync == 1)
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{
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//errors caused due to playing MBE files out of sync, break loop
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if (state->errs > 2 || state->errsR > 2)
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{
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//goto END; //
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}
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//errors caused due to playing MBE files out of sync, break loop
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if (state->errs2 > 4 || state->errs2R > 4)
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{
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goto END; //
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}
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}
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//earlier skip conditions teleport us here to process further skip conditions before restarting while loop
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SKIP:
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if (skipcount > 2) //after 2 consecutive data frames, drop back to getFrameSync and process with processDMRdata
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{
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goto END;
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}
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//since we are in a while loop, run ncursesPrinter here.
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if (opts->use_ncurses_terminal == 1)
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{
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ncursesPrinter(opts, state);
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}
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} // while loop
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//Teleport here on END condition, set or reset variables and return to look for new frame sync
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END:
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state->dmr_stereo = 0;
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state->errs2R = 0;
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state->errs2 = 0;
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}
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//Process buffered half frame and 2nd half and then jump to full BS decoding
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void dmrBSBootstrap (dsd_opts * opts, dsd_state * state)
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{
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int i, j, k, l, dibit;
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int *dibit_p;
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char ambe_fr[4][24] = {0};
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char ambe_fr2[4][24] = {0};
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char ambe_fr3[4][24] = {0};
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const int *w, *x, *y, *z;
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char sync[25];
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char syncdata[48];
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char cachdata[13] = {0};
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int mutecurrentslot;
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int msMode;
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char cc[4];
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unsigned char EmbeddedSignalling[16];
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unsigned int EmbeddedSignallingOk;
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//add time to mirror printFrameSync
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time_t now;
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char * getTime(void) //get pretty hh:mm:ss timestamp
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{
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time_t t = time(NULL);
|
|
|
|
char * curr;
|
|
char * stamp = asctime(localtime( & t));
|
|
|
|
curr = strtok(stamp, " ");
|
|
curr = strtok(NULL, " ");
|
|
curr = strtok(NULL, " ");
|
|
curr = strtok(NULL, " ");
|
|
|
|
return curr;
|
|
}
|
|
|
|
//payload buffer
|
|
//CACH + First Half Payload + Sync = 12 + 54 + 24
|
|
dibit_p = state->dibit_buf_p - 90; //this seems to work okay for both
|
|
//dibit_p = state->dmr_payload_p - 90;
|
|
for (i = 0; i < 90; i++) //90
|
|
{
|
|
dibit = *dibit_p;
|
|
dibit_p++;
|
|
if(opts->inverted_dmr == 1)
|
|
{
|
|
dibit = (dibit ^ 2);
|
|
}
|
|
state->dmr_stereo_payload[i] = dibit;
|
|
}
|
|
|
|
for(i = 0; i < 12; i++)
|
|
{
|
|
dibit = state->dmr_stereo_payload[i];
|
|
cachdata[i] = dibit;
|
|
if(i == 2)
|
|
{
|
|
state->currentslot = (1 & (dibit >> 1));
|
|
}
|
|
}
|
|
|
|
//Setup for first AMBE Frame
|
|
|
|
//Interleave Schedule
|
|
w = rW;
|
|
x = rX;
|
|
y = rY;
|
|
z = rZ;
|
|
|
|
//First AMBE Frame, Full 36
|
|
for(i = 0; i < 36; i++)
|
|
{
|
|
dibit = state->dmr_stereo_payload[i+12];
|
|
ambe_fr[*w][*x] = (1 & (dibit >> 1)); // bit 1
|
|
ambe_fr[*y][*z] = (1 & dibit); // bit 0
|
|
|
|
w++;
|
|
x++;
|
|
y++;
|
|
z++;
|
|
|
|
}
|
|
|
|
//Setup for Second AMBE Frame
|
|
|
|
//Interleave Schedule
|
|
w = rW;
|
|
x = rX;
|
|
y = rY;
|
|
z = rZ;
|
|
|
|
//Second AMBE Frame, First Half 18 dibits just before Sync or EmbeddedSignalling
|
|
for(i = 0; i < 18; i++)
|
|
{
|
|
dibit = state->dmr_stereo_payload[i+48];
|
|
ambe_fr2[*w][*x] = (1 & (dibit >> 1)); // bit 1
|
|
ambe_fr2[*y][*z] = (1 & dibit); // bit 0
|
|
|
|
w++;
|
|
x++;
|
|
y++;
|
|
z++;
|
|
|
|
}
|
|
|
|
// signaling data or sync, just redo it
|
|
for(i = 0; i < 24; i++)
|
|
{
|
|
dibit = state->dmr_stereo_payload[i+66];
|
|
sync[i] = (dibit | 1) + 48;
|
|
}
|
|
sync[24] = 0;
|
|
//this method seems to work to make sure we aren't in a data sync especially when inverted signal
|
|
//consider only testing this when inverted signal if this causes issues with sync later on
|
|
if ( strcmp (sync, DMR_BS_VOICE_SYNC) != 0)
|
|
{
|
|
goto END;
|
|
}
|
|
|
|
//Continue Second AMBE Frame, 18 after Sync or EmbeddedSignalling
|
|
for(i = 0; i < 18; i++)
|
|
{
|
|
dibit = getDibit(opts, state);
|
|
ambe_fr2[*w][*x] = (1 & (dibit >> 1)); // bit 1
|
|
ambe_fr2[*y][*z] = (1 & dibit); // bit 0
|
|
|
|
w++;
|
|
x++;
|
|
y++;
|
|
z++;
|
|
|
|
}
|
|
|
|
//Setup for Third AMBE Frame
|
|
|
|
//Interleave Schedule
|
|
w = rW;
|
|
x = rX;
|
|
y = rY;
|
|
z = rZ;
|
|
|
|
//Third AMBE Frame, Full 36
|
|
for(i = 0; i < 36; i++)
|
|
{
|
|
dibit = getDibit(opts, state);
|
|
ambe_fr3[*w][*x] = (1 & (dibit >> 1)); // bit 1
|
|
ambe_fr3[*y][*z] = (1 & dibit); // bit 0
|
|
|
|
w++;
|
|
x++;
|
|
y++;
|
|
z++;
|
|
|
|
}
|
|
|
|
fprintf (stderr,"%s ", getTime());
|
|
if (opts->inverted_dmr == 0)
|
|
{
|
|
fprintf (stderr,"Sync: +DMR | Frame Sync | DMRSTEREO | VC1 ");
|
|
if ( (state->K > 0 && state->dmr_so & 0x40 && state->payload_keyid == 0) ||
|
|
(state->K > 0 && state->dmr_soR & 0x40 && state->payload_keyidR == 0) )
|
|
{
|
|
fprintf (stderr, "%s", KYEL);
|
|
fprintf(stderr, " BPK %lld", state->K);
|
|
fprintf (stderr, "%s", KNRM);
|
|
//state->currentslot = 0; //slot now set from cach data from buffer
|
|
}
|
|
fprintf (stderr, "\n");
|
|
}
|
|
else
|
|
{
|
|
fprintf (stderr,"Sync: -DMR | Frame Sync | DMRSTEREO | VC1 ");
|
|
if ( (state->K > 0 && state->dmr_so & 0x40 && state->payload_keyid == 0) ||
|
|
(state->K > 0 && state->dmr_soR & 0x40 && state->payload_keyidR == 0) )
|
|
{
|
|
fprintf (stderr, "%s", KYEL);
|
|
fprintf(stderr, " BPK %lld", state->K);
|
|
fprintf (stderr, "%s", KNRM);
|
|
//state->currentslot = 0; //slot now set from cach data from buffer
|
|
}
|
|
fprintf (stderr, "\n");
|
|
}
|
|
|
|
//these ambe_fr values are set correctly now!
|
|
//reset drop values since we don't know which slot (because I'm too lazy to write that part)
|
|
state->dropL = 256;
|
|
state->dropR = 256;
|
|
processMbeFrame (opts, state, NULL, ambe_fr, NULL);
|
|
processMbeFrame (opts, state, NULL, ambe_fr2, NULL);
|
|
processMbeFrame (opts, state, NULL, ambe_fr3, NULL);
|
|
dmrBS (opts, state); //bootstrap into full TDMA frame for BS mode
|
|
END:
|
|
//placing this below to fix compiler error, it will never run but compiler needs something there
|
|
if (0 == 1)
|
|
{
|
|
fprintf (stderr, "this is a dumb thing to have to fix");
|
|
}
|
|
|
|
}
|